Along with the advancement of semiconductor fabrication technology and the continuous improvement in circuit functionality of chips, in order to satisfy requirements for various effectively developed portable products in the fields of communications, networks and computers, semiconductor packages capable of reducing an IC (integrated circuit) area and having high density and multiple leads, such as ball grid array (BGA) packages, flip-chip (FC) packages, chip size packages (CSPs) and multi chip modules (MCMs), have become mainstream package products.
In the semiconductor packaging technology applied to an advanced product such as a memory, a semiconductor package with a central-pad chip is generally adopted and capable of reducing the length of bonding wires to improve the electrical quality of signal transmission. Accordingly, the IBM (International Business Machines) Corporation has proposed a lead-on-chip (LOC) package by U.S. Pat. No. 4,862,245, which utilizes a plurality of leads of a lead frame to provide external signal transmission for a chip incorporated in the package. Although this LOC package structure avoids the use of a substrate and is relatively more economically beneficial, the signal transmission path through the leads is considered lengthy and may adversely affect the electrical quality, making such package structure not suitable for products having a frequency over 500 MHz such as DRAM (dynamic random access memory), SDRAM (synchronous DRAM), DDR SDRAM (double data-rate SDRAM), etc. Moreover, since the leads of the lead frame are used to provide the external signal transmission for the chip, this sets a limitation on the number of input/output (I/O) connections that can be disposed on a unit area, and thus the package structure is not suitably applied to the foregoing high-frequency products.
In order to satisfy the requirements of electrical quality and high I/O connections for the foregoing high-frequency products, there has been developed a window ball grid array (WBGA) package structure, which uses a substrate having at least one opening therethrough, and allows a chip to be mounted on an upper surface of the substrate and cover the opening in a face-down manner, with a plurality of bonding wires (gold wires) being received in the opening to electrically connect the chip to a lower surface of the substrate. This WBGA package structure can further effectively reduce the length of the leads mentioned above to thereby improve the electrical transmission quality between the chip and the substrate, and thus has been widely applied to a semiconductor package with a chip having central pads such as DRAM.
U.S. Pat. No. 6,218,731 has disclosed a WBGA semiconductor package. As shown in FIG. 1, this semiconductor package 1 comprises a substrate 11 having a central opening 111; a chip 12 mounted on an upper surface of the chip 11 via an adhesive layer 123 in a face-down manner that bond pads 122 formed on an active surface 121 of the chip 12 are exposed to the opening 111; a plurality of bonding wires 13 formed in the opening 111, for electrically connecting the chip 12 to the substrate 11, such that the bond pads 122 of the chip 12 are electrically connected to a lower surface of the substrate 11; a first encapsulant 14 formed on the upper surface of the substrate 11 to encapsulate the chip 12; a second encapsulant 141 formed on the lower surface of the substrate 11 and filling the opening 111; and a plurality of solder balls 15 implanted at a plurality of ball pads 151 located on areas of the lower surface of the substrate 11 not having the second encapsulant 141, the solder balls 15 for being electrically connected to an external electronic device.
For the cost concern, the above conventional semiconductor package 1 is usually fabricated in a batch manner that a substrate strip comprising a plurality of the substrates 11 arranged in an array is used to form and mold a plurality of package units thereon, and then the package units are subjected to a singulation process. As shown in FIG. 2, after the die-bonding and wire-bonding processes have been completed for the array-arranged substrates 11, the substrate strip is placed into an encapsulating mold 16 and clamped between an upper mold 161 and a lower mold 162 of the encapsulating mold 16. Then, conventional steps of mold engagement, resin injection and curing are performed, such that the first encapsulant 14 is formed on the upper surface of the substrate strip to encapsulate all of the chips 12 mounted on the substrates 11, and the second encapsulant 141 is formed on the lower surface of each of the substrates 11 to encapsulate the bonding wires 13 received in the opening 111 of each of the substrates 11. Subsequently, a ball-implanting process and a singulation process are carried out to form a plurality of individual WBGA semiconductor packages 1.
However, the foregoing conventional WBGA semiconductor package 1 has a structural limitation that wire loops of the bonding wires 13 must be protruded from the lower surface of the substrate 11, and thus the second encapsulant 141 for encapsulating the bonding wires 13 would be further protruded on the lower surface of the substrate 11. As a result, different lower molds 162 are required in response to different structures of openings 111 of various substrates 11, thereby effectively increasing the fabrication cost.
Moreover, since positions on the substrate 11 predetermined for forming the first encapsulant 14 and the second encapsulant 141 do not exactly correspond to each other, the upper and lower molds 161, 162 may not be able to firmly clamp the substrate 11 therebetween and thus cause flashes of the second encapsulant 141 on the lower surface of the substrate 11. This not only impairs the exterior appearance of the semiconductor package 1 but also may affect the process of implanting solder balls 15 and the electrical quality thereof if ball pads on the lower surface of the substrate 11 are contaminated by the resin flashes. As such, an additional deflash process is required to remove the resin flashes by using solvents, thereby making the fabrication processes complicated, and also the issue of contaminating the ball pads is raised.
In order to completely encapsulate the wire loops of the bonding wires 13, the second encapsulant 141 usually occupies an excessively large area on the substrate 11, and this would limit the number and density of the solder balls 15 or I/O connections capable of being arranged on the substrate 11. Furthermore, in order not to affect a subsequent reflow-soldering process, the height of the solder balls 15 must be greater than a distance between a bottom surface of the second encapsulant 141 and the lower surface of the substrate 11. This height requirement also governs the diameter of the solder balls 15 and sets a further limitation on the number of solder balls 15 capable of being disposed on the lower surface of the substrate 11. As a result, the even less I/O connections can be accommodated in the semiconductor package 1.
Additionally, in the foregoing conventional WBGA semiconductor package 1, heat produced by operation of the chip 12 is indirectly conducted outwards through the substrate 11. Such indirect heat transmitting path does not provide any mechanism for actively improving the heat dissipating efficiency. Thus, the WBGA semiconductor package 1 if being applied to a high-frequency product may easily degrade electrical performances due to unsatisfactory heat dissipating effect.
Therefore, the problem to be solved here is to provide a semiconductor packaging technology, which can resolve the above drawbacks in the prior art to improve the heat dissipating efficiency and electrical quality, without having to fabricate different lower molds in response to different structures of substrate openings, thereby increasing the yield of the overall fabrication processes, simplifying the fabrication processes, and reducing the fabrication cost.